A centralized infrastructure repository for QREM RTL hardware development.

QREM Top Level Controller FSM Unit

The memory plane for the QREM ML-KEM accelerator. Features 4-bank polynomial SRAM, deterministic 2-port scheduling, a dual-port seed store, and secure wipe FSMs.

High-performance QREM ML-KEM Transcoder Unit. Handles structural formatting, polynomial compression, and datapath orchestration.

A high-performance SystemVerilog implementation of polynomial samplers for lattice-based cryptography, specifically targeting the FIPS 203 ML-KEM (Kyber) standard. This repository provides efficient, pipelined hardware modules for SampleNTT and SamplePolyCBD.

Highly Optimized Polynomial Arithmetic Unit (PAU) for QREM, designed to accelerate the core mathematical operations required by the NIST FIPS 203 (ML-KEM / Kyber) post-quantum cryptography standard.

A unified hardware accelerator for QREM ML-KEM hashing and sampling, tightly coupling Keccak cores with polynomial samplers to minimize memory overhead and latency.

A FIPS 202 compliant SystemVerilog implementation of the Keccak permutation (SHA-3/SHAKE). Features a high-frequency multi-cycle architecture, runtime-configurable modes (SHA3-256/512, SHAKE128/256), and standard AXI4-Stream interfaces with full backpressure support. Verified using official NIST test vectors.

Shared RTL Library for QREM Modules