AS16: A 16-bit RISC CPU

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The AS16 is a custom 16-bit RISC processor implemented in Verilog for the wafer.space GF180MCU Run 2 shuttle. It features hardware predication, a 16-entry general register file, and a 6-state FSM controller.

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Hardware Interface

module as16(
    input [15:0] datain,
    output [15:0] dataout,
    output [15:0] address,
    output rnw,
    input clk,
    input reset_b
);

• datain / dataout: 16-bit parallel data buses
• address: 16-bit memory address pointer (PC_q or OR_q)
• rnw: read/not-write control signal, active low during writes
• clk / reset_b: rising-edge clock and asynchronous active-low reset

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Instruction Format

Supports 16-bit single-word or 32-bit double-word layout based on length bit l.

 ppp l oooo ssss dddd   wwwwwwwwwwwwwwww
  │  │   │    │    │            │
  │  │   │    │    │            └─ 16b optional operand word
  │  │   │    │    └──────────────  4b source/destination register
  │  │   │    └───────────────────  4b source register
  │  │   └────────────────────────  4b opcode
  │  └────────────────────────────  1b instruction length
  └───────────────────────────────  3b predicate bits

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Architecture & Registers

• Registers: 16 x 16b GRF. R0 hardwired to 0. R15 acts as Program Counter (PC_q).
• Special Registers: Instruction Register (IR_q) and Operand Register (OR_q).
• Predication: Dynamic instruction skipping using bits [15:13] against Carry (C_q) and Zero flags.

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Instruction Set Architecture (ISA)

The ALU selects its operations using bits [10:8] of the instruction register.

Opcode	Mnemonic	Operation	Description
3'b000	LD	result = OR_q	load value of operand register to destination register
3'b001	ADD	result = register + OR_q	add source register to operand register
3'b010	AND	result = register & OR_q	bitwise AND between register and operand register
3'b011	OR	result = register | OR_q	bitwise OR between register and operand register
3'b100	XOR	result = register ^ OR_q	bitwise XOR between register and operand register
3'b101	ROR	rotate right with carry	rotates operand register right by one bit through carry flag
3'b110	ADC	result = register + OR_q + C_q	add with carry flag input
3'b111	STO	memory[OR_q] = register	store source register value out to memory address in OR_q

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Execution States (FSM)

1. FETCH0: fetch base opcode word
2. FETCH1: fetch 16-bit immediate extension word if needed
3. EA_ED: calculate effective memory addresses
4. RDMEM: read data from external memory
5. EXEC: execute ALU operation and write back to registers
6. WRMEM: write data to memory (rnw goes low)

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Below is simply the README from the template:

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gf180mcu Project Template

Project template for wafer.space MPW runs using the gf180mcu PDK.

Dependencies

Too manage all dependencies, the project template includes a Nix shell with all the required tools. Install Nix and LibreLane by following the Nix-based installation instructions: https://librelane.readthedocs.io/en/latest/installation/nix_installation/index.html To activate the shell, simply run nix-shell in the root directory of this repository. The subsequent steps assume that you are in the Nix shell of the project template.

Prerequisites

The project template uses the open_pdks gf180mcuD variant of the PDK. To clone the latest PDK version via Ciel, run make clone-pdk.

Implement the Design

With the Nix shell enabled, run the implementation:

make librelane

You can find all output artifacts in the librelane/runs/<timestamp>/ directory.

View the Design

After completion, you can view the design using the OpenROAD GUI:

make librelane-openroad

Or using KLayout:

make librelane-klayout

Verification and Simulation

For the verification of the chip we use cocotb. Cocotb is a Python-based testbench environment. The simulator that is used by the project template is Icarus Verilog.

The testbench is located in cocotb/chip_top_tb.py. To run the RTL simulation, run the following command:

make sim

To run the GL (gate-level) simulation, run the following command:

make sim-gl

Note

You need to have the latest implementation of your design in the final/ folder. After a run has completed without errors, the final views will be copied to final/.

In both cases, a waveform file will be generated under cocotb/sim_build/chip_top.fst. You can view it using a waveform viewer, for example, GTKWave.

make sim-view

You can now update the testbench according to your design.

Implementing Your Own Design

The source files for this template can be found in the src/ directory. chip_top.sv defines the top-level ports and instantiates chip_core, chip ID (QR code) and the wafer.space logo. To allow for the default bonding setup, do not change the number of pads in order to keep the original bondpad positions. To be compatible with the default breakout PCB, do not change any of the power or ground pads. However, you can change the type of the signal pads, e.g. to bidirectional, input-only or e.g. analog pads. The template provides the NUM_INPUT and NUM_BIDIR parameters for this purpose.

The actual pad positions are defined in the LibreLane configuration file under librelane/config.yaml. The variables PAD_SOUTH/PAD_EAST/PAD_NORTH/PAD_WEST determine the respective pad placement. The LibreLane configuration also allows you to customize the flow (enable or disable steps), specify the source files, set various variables for the steps, and instantiate macros. For more information about the configuration, please refer to the LibreLane documentation: https://librelane.readthedocs.io/en/latest/

To implement your own design, simply edit chip_core.sv. The chip_core module receives the clock and reset, as well as the signals from the pads defined in chip_top. As an example, a 42-bit wide counter is implemented.

Note

For more comprehensive SystemVerilog support, enable the USE_SLANG variable in the LibreLane configuration.

Choosing a Different Slot Size

The template supports the following slot sizes: 1x1, 0p5x1, 1x0p5, 0p5x0p5. By default, the design is implemented using the 1x1 slot definition.

To select a different slot size, simply set the SLOT environment variable. This can be done when invoking a make target:

SLOT=0p5x0p5 make librelane

Alternatively, you can export the slot size:

export SLOT=0p5x0p5

You can change the slot that is selected by default in the Makefile by editing the value of DEFAULT_SLOT.

Select Different IP Libraries

The project template has support for selecting libraries with the below environment variables:

Env	Available Values	Description
SCL	gf180mcu_fd_sc_mcu7t5v0, gf180mcu_fd_sc_mcu9t5v0, gf180mcu_as_sc_mcu7t3v3	The standard cell library.
PAD	gf180mcu_fd_io, gf180mcu_ocd_io	The I/O pad library.
SRAM	gf180mcu_fd_ip_sram, gf180mcu_ocd_ip_sram	The SRAM library.

For example, to build the 0p5x0p5 chip with 3v3 libraries:

SLOT=0p5x0p5 SCL=gf180mcu_as_sc_mcu7t3v3 PAD=gf180mcu_ocd_io SRAM=gf180mcu_ocd_ip_sram make librelane

The default values can be changed in the Makefile.

Note

Not all of the community-created IPs have been tested yet, so support for them is experimental!

Building a Standalone Padring for Analog Design

To build just the padring without any standard cell rows, digital routing or filler cells, run the following command:

make librelane-padring

It is also possible to build the padring for other slot sizes:

SLOT=0p5x0p5 make librelane-padring

Precheck

To check whether your design is suitable for manufacturing, run the gf180mcu-precheck with your layout.