missing VMI features for high-perf simd kernels#997
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…, UE8M0, Persistent Co-authored-by: Cursor <cursoragent@cursor.com>
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…hecks Align gaps with remaining VMI vs ASC BW blockers; add small-L ui8 widen; check in lowered VPTO for working workarounds.
Name the compiling-today path for what it is: correct but slow.
Cover MHC-style continuous bf16 strips (EVEN-only UNPK today; dist_mode=unpack illegal). Note cast-back as a 05 consumer.
Add minimal reference_asc_cce.asc kernels that compile on the Ascend CCE path while target_mi HIVM still crashes on bisheng.
Express dual-buffer ping-pong and pipe-event sync in target_mi for gap 05 (still fails HIVM/bisheng). Retarget gap 06 MI to PAT_VL8; that shape now builds with bisheng while VMI L=8 legalization remains the gap.
Pair current_slow_vmi.py / desired_vmi.py with each gap IR so the VMI authoring surface is documented alongside the .pto reproducers.
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See standalone docs & reproducers in
docs/feature-gaps/vmi.This is a bug report & feature request, not a mergeable PR.
Suggested priority (for highest perf gain): 03, 05, 06; then 07, 01, 02
@mouliangyu @Zhendong404 @WenboCodes