This repository was archived by the owner on Jan 5, 2026. It is now read-only.

All issues

[Feature request] adding FHDL module to synthesizable VHDL support

#311

· ohault opened

on May 30, 2025

Invalid verilog representation

#308

· ollie-etl opened

on May 6, 2025

VCD file may contain time stamps as floats

#306

· oscargus opened

on Apr 16, 2025

`fsm.delayed_enter` incompatible with vcd dump

#305

· enurseitov opened

on Apr 15, 2025

Support for negedge sensitivity list

#304

· shantzis62 opened

on Apr 12, 2025

assignment of combinatorial values with delayed assignment gives incorrect results when referencing same signal

#303

· jwise opened

on Mar 11, 2025

Support for python 3.13

#297

· jasonbridges opened

on Dec 2, 2024

Async FIFO Output is Broken when FIFO Depth is Set to 2

#296

· linuswck opened

on Nov 15, 2024

`else` branch elided in generated Verilog

#274

· McSherry opened

on Jun 22, 2023

Better FMC support

#269

· kaolpr opened

on Nov 25, 2022

[Sim] Error with fsm delayed_enter method

#267

· kamejoko80 opened

on Oct 7, 2022

move the conditional part of `toolchain.build(run=True/False)` to a separate method

#258

· lneuhaus opened

on Feb 22, 2022