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pipelined-cpu

Here are 3 public repositories matching this topic...

SalehHijazi / MIPS-Pipeline-CPU

A synthesizable 5-stage pipelined MIPS CPU and SoC architecture implemented in Verilog. Features advanced hardware hazard mitigation (data forwarding & load-use stalling), an expanded ISA (JAL, shifts, logical immediates), self-checking testbenches, and Xilinx FPGA readiness.

verilog digital-logic computer-architecture mips-processor hardware-verification rtl-design soc-design pipelined-cpu fpga-ready

Updated Jan 3, 2026
Verilog

simplified-risc-xl

SudheerVadrevu / simplified-risc-xl

A fully modular, pipelined 32-bit RISC processor built using Verilog with testbenches and ASIC-ready structure. Part of master's coursework at BTH.

verilog digital-logic computer-architecture risc-processor asic-design pipelined-cpu bth-sweden

Updated Jul 15, 2025
Verilog

Zhungg / rv32i-cpu-openlane

RV32I 5-stage pipelined CPU core implemented in SystemVerilog and taken through a complete Sky130A RTL-to-GDSII flow using OpenLane 2 and OpenROAD.

Updated Jul 24, 2026
SystemVerilog

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