This project presents a scalable, high-performance VLSI router architecture for Network-on-Chip (NoC) platforms, using Code Division Multiple Access (CDMA) to enable concurrent data transfers with reduced latency and power consumption. Built with Verilog HDL and implemented on an Artix-7 FPGA.

RTL Design and Verification of a Parameterized Synchronous FIFO in Verilog with directed, corner, and randomized test cases.

Parameterized 16-bit ALU designed in Verilog HDL with functional verification, synthesis, RTL schematic, and gate-level netlist.

RTL design and functional verification of a 32-bit ALU using Verilog HDL. Supports arithmetic, logical, and shift operations with corner-case handling such as divide-by-zero, underflow, and tri-state output enable. Simulated and verified using Xilinx ISE.

In this repo, I have designed a 4-2 compressor and 3-2 compressor based 8x8 dadda multiplier

FPGA-based smart home automation controller using Verilog HDL featuring automated lighting, temperature-based appliance control, security alarm logic, and simulation-based verification.

5-Stage RISC-V Pipelined Processor designed in Verilog HDL featuring Instruction Fetch, Decode, Execute, Memory Access, and Write-Back stages with RTL simulation and verification.

This repository contains the report of the Week 3 task for VSD RV SoC Tapeout Program

A collection of 5 RTL digital design modules implemented in Verilog and simulated using ModelSim — covering UART, FIFO, Traffic Light Controller, Automatic Temperature Control, and Washing Machine Controller, each designed using FSM-based architecture with draw.io block diagrams, state transition tables, and waveform verification.

Actively developing projects in VHDL, Verilog RTL-to-bitstream flow and FPGA prototyping on Cmod A7 (Xilinx Artix-7 35T) FPGA board, in Xilinx Vivado 2024.1. Knowledge of protocols including UART, SPI, I²C, and AXI-lite.