Skip to content

Fix fpga chip passing gate's internal table instead of chip entity to output function#3656

Merged
Astralcircle merged 1 commit into
wiremod:masterfrom
Astralcircle:cantool
Jul 17, 2026
Merged

Fix fpga chip passing gate's internal table instead of chip entity to output function#3656
Astralcircle merged 1 commit into
wiremod:masterfrom
Astralcircle:cantool

Conversation

@Astralcircle

Copy link
Copy Markdown
Contributor

Because of this all gates that used WireLib.CanTool did not work in FPGA

… output function

Because of this all gates that used WireLib.CanTool did not work in FPGA
@Astralcircle
Astralcircle merged commit 6fdc26a into wiremod:master Jul 17, 2026
1 check passed
@Astralcircle
Astralcircle deleted the cantool branch July 17, 2026 00:32
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant